98 lines
2.6 KiB
ArmAsm
98 lines
2.6 KiB
ArmAsm
#include "textflag.h"
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#define Rdst R0
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#define Rsrc R1
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#define Rlen R2
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#define Rwr R3
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#define Rrem R4
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#define Rtmp R5
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#define Vlut V0
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#define Vfld0 V6
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#define Vfld1 V7
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#define Vfld2 V8
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#define Vfld3 V9
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#define Vsrc0 V10
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#define Vsrc1 V11
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#define Vsrc2 V12
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#define Vr0a V13
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#define Vr1a V14
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#define Vr2a V15
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#define Vr3a V16
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#define Vr0b V17
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#define Vr1b V18
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#define Vr2b V19
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#define Vr3b V20
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// func encodeARM64(dst []byte, src []byte, lut *int8) (int, int)
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TEXT ·encodeARM64(SB),NOSPLIT,$0-72
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// Load dst/src info
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MOVD dst_base+0(FP), Rdst
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MOVD src_base+24(FP), Rsrc
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MOVD src_len+32(FP), Rlen
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MOVD lut+48(FP), Rtmp
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VLD1 (Rtmp), [Vlut.B16]
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MOVD Rlen, Rrem
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MOVD Rdst, Rwr
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VMOVI $51, V1.B16
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VMOVI $26, V2.B16
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VMOVI $63, V3.B16
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VMOVI $13, V4.B16
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loop:
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VLD3.P 48(Rsrc), [Vsrc0.B16, Vsrc1.B16, Vsrc2.B16]
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// Split 3 source blocks into 4 lookup inputs
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VUSHR $2, Vsrc0.B16, Vfld0.B16
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VUSHR $4, Vsrc1.B16, Vfld1.B16
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VUSHR $6, Vsrc2.B16, Vfld2.B16
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VSHL $4, Vsrc0.B16, Vsrc0.B16
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VSHL $2, Vsrc1.B16, Vsrc1.B16
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VORR Vsrc0.B16, Vfld1.B16, Vfld1.B16
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VORR Vsrc1.B16, Vfld2.B16, Vfld2.B16
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VAND V3.B16, Vfld1.B16, Vfld1.B16
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VAND V3.B16, Vfld2.B16, Vfld2.B16
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VAND V3.B16, Vsrc2.B16, Vfld3.B16
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WORD $0x6e212ccd // VUQSUB V1.B16, Vfld0.B16, Vr0a.B16
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WORD $0x4e263451 // VCMGT V2.B16, Vfld0.B16, Vr0b.B16
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VAND V4.B16, Vr0b.B16, Vr0b.B16
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VORR Vr0b.B16, Vr0a.B16, Vr0a.B16
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WORD $0x6e212cee // VUQSUB V1.B16, Vfld1.B16, Vr1a.B16
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WORD $0x4e273452 // VCMGT V2.B16, Vfld1.B16, Vr1b.B16
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VAND V4.B16, Vr1b.B16, Vr1b.B16
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VORR Vr1b.B16, Vr1a.B16, Vr1a.B16
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WORD $0x6e212d0f // VUQSUB V1.B16, Vfld2.B16, Vr2a.B16
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WORD $0x4e283453 // VCMGT V2.B16, Vfld2.B16, Vr2b.B16
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VAND V4.B16, Vr2b.B16, Vr2b.B16
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VORR Vr2b.B16, Vr2a.B16, Vr2a.B16
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WORD $0x6e212d30 // VUQSUB V1.B16, Vfld3.B16, Vr3a.B16
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WORD $0x4e293454 // VCMGT V2.B16, Vfld3.B16, Vr3b.B16
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VAND V4.B16, Vr3b.B16, Vr3b.B16
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VORR Vr3b.B16, Vr3a.B16, Vr3a.B16
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// Add result of lookup table to each field
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VTBL Vr0a.B16, [Vlut.B16], Vr0a.B16
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VADD Vr0a.B16, Vfld0.B16, Vfld0.B16
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VTBL Vr1a.B16, [Vlut.B16], Vr1a.B16
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VADD Vr1a.B16, Vfld1.B16, Vfld1.B16
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VTBL Vr2a.B16, [Vlut.B16], Vr2a.B16
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VADD Vr2a.B16, Vfld2.B16, Vfld2.B16
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VTBL Vr3a.B16, [Vlut.B16], Vr3a.B16
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VADD Vr3a.B16, Vfld3.B16, Vfld3.B16
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VST4.P [Vfld0.B16, Vfld1.B16, Vfld2.B16, Vfld3.B16], 64(Rwr)
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SUB $48, Rrem
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CMP $48, Rrem
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BGE loop
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done:
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SUB Rdst, Rwr
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SUB Rrem, Rlen
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MOVD Rwr, ret+56(FP)
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MOVD Rlen, ret1+64(FP)
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RET
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